1. Field of the Invention
The present invention relates to an image sensing apparatus which performs image sensing with an image sensing element in which charges can be sequentially transferred in a horizontal direction, and a control method therefor.
2. Description of the Related Art
In recent years, an image sensing apparatus such as an electronic camera which records/plays still images or moving images sensed by an image sensing element such as a CCD, with a memory card having a memory element as a recording medium has been actively developed and commercially available. Here, a common configuration and an operation example of an image input section of a conventional digital camera will be described with reference to FIGS. 10 to 13.
FIG. 10 is a block diagram showing the configuration of the image input section of the conventional digital camera. FIG. 11 is a diagram showing a configuration of a horizontal transfer final stage section of a CCD 1001 in FIG. 10. FIG. 12 is a diagram showing a control timing of a sample-hold circuit. FIG. 13 is a block diagram showing a detailed configuration of a CDS circuit 1002 in FIG. 10.
In FIG. 10, the digital camera is provided with the CCD 1001 which is the image sensing element, a correlated double sampling (hereinafter referred to as “CDS”) circuit 1002, an amplifier 1003, an analog-digital converter (hereinafter referred to as “ADC”) 1004 and a CCD driving section 1005. The CCD 1001 is driven by respective driving pulse signals such as a horizontal transfer pulse, a reset gate pulse, a vertical transfer pulse and an electronic shutter pulse which are outputted from the CCD driving section 1005, and converts an optical image of an object into an electrical signal.
Within the CCD 1001 which performs horizontal charge transfer driving in a three-phase driving manner, charges exposed and accumulated by a light receiving element are sequentially transferred on a pixel by pixel basis in a horizontal direction by the horizontal transfer pulse. As shown in FIG. 11, the charges are eventually transferred from a horizontal transfer pulse H2 section 1100 to a horizontal transfer pulse H3 section 1101, and to a horizontal transfer pulse H1 section 1102. Subsequently, the charges pass through a horizontal final stage 1103, and are transferred to a floating diffusion (FD) section 1104, then converted into a voltage signal, and sequentially outputted as a video signal per pixel. After being converted into the voltage signal, the charges are swept (discarded) into a drain section 1106 by turning ON a reset gate 105.
In this way, the signal outputted from the CCD 1001 requires a reset operation per pixel. This reset operation causes a reset flaw to be generated in the output signal of the CCD 1001.
FIG. 12 shows a relationship between the reset gate pulse (RG) and the reset flaw, and the control timing of the sample-hold circuit for extracting a level of a feed-through section and a level of an optical output signal section, respectively, in one pixel cycle of the output signal of the CCD 1001. The output signal of the CCD 1001 is basically composed of the reset flaw generated from the reset gate pulse, the feed-through level which becomes a black reference per pixel, and the optical output signal level proportional to an amount of light.
Returning to FIG. 10, the CDS circuit 1002 is a noise removal circuit for removing a co-related noise component from the output signal by obtaining a difference between the level of the feed-through section and the level of the optical output signal section in the output signal of the CCD 1001.
As shown in FIG. 13, a common CDS circuit is configured with sample-hold circuits 1301 and 1302 which are connected in series, a sample-hold circuit 1303, and a differential amplifier 1304. An SHP is a pulse signal for sample-holding a feed-through period for retaining a reset level. An SHD is a pulse signal for sample-holding an optical output signal period. The CDS circuit is configured to sample-hold the output signal of the CCD with the SHP and the SHD by the sample-hold circuits 1301, 1302 and 1303, and to take a difference between respective outputs of the sample-hold circuits 1302 and 1303 by the differential amplifier 1304.
Returning to FIG. 10, an output signal of the CDS circuit 1002 is amplified to a specified signal level in accordance with an input range of the ADC 1004 by the amplifier 1003. An output signal of the amplifier 1003 is converted into a digital signal by the ADC 1004, and subsequently further transmitted to a digital signal processing circuit (not shown) at a subsequent stage.
The image sensing apparatus such as the above described digital camera has tended to increase resolutions or an operating speed related to shooting year by year in response to market needs for higher image quality for enhancing the quality of images or increase in the number of pixels for increasing the pixels. Most models of the image sensing apparatus with increased resolutions or operating speed have a high-speed continuous shooting function, a live view function (function of focusing or the like while displaying a sensed image in real time), and further a moving image function. Thus, a high CCD driving frequency is required for satisfying these functions (specifications).
On the other hand, the high CCD driving frequency set in the image sensing apparatus causes a harmful effect in which timing margins of the feed-through period (TP) and the optical output signal period (TD) shown in FIG. 12 are reduced. Thus, stability of the sample-hold of each signal is decreased, and a signal-to-noise ratio (S/N) property may be degraded.
As a countermeasure against the degradation of the S/N property, there is a method of setting phases and pulse widths so as to increase the timing margin of the feed-through period or the optical output signal period. For example, it becomes possible to take a large timing margin of the feed-through period (TP) or the optical output signal period (TD) by setting a small pulse width of the reset gate pulse among the respective CCD driving pulse signals (for example, see Japanese Laid-Open Patent Publication (Kokai) No. 2006-42261).
However, as the above described conventional art, as the countermeasure against the degradation of the S/N property, if the phases and the pulse widths have been set so that the timing margins of the feed-through period and the optical output signal period can be secured, the following problem occurs. In other words, as a harmful effect of the countermeasure against the degradation of the S/N property, a defective reset may be generated in the case of handling a large charge at a horizontal final stage section of the CCD. A reason thereof will be described by using FIGS. 12, 3 and 6.
FIGS. 6A to 6C show charge transfer states at the horizontal transfer final stage section of the three-phase driving in the CCD. FIG. 3A is a diagram showing a phase relationship between a horizontal transfer pulse H3 and the reset gate pulse which are CCD driving pulse signals in a still image recording operation mode of the digital camera, and FIG. 3B is a diagram showing a waveform of the CCD output signal. FIG. 3C is a diagram showing a phase relationship among a horizontal transfer pulse H1, the horizontal transfer pulse H3 and a horizontal transfer pulse H2 which are the CCD driving pulse signals. In other words, FIG. 3A shows the phase relationship between a horizontal transfer pulse HS 303 and a reset gate pulse (RG) 301, and FIG. 3C shows the phase relationship among a horizontal transfer pulse H1 302, the horizontal transfer pulse H3 303 and a horizontal transfer pulse H2 304.
In order to secure the timing margins of the feed-through period and the optical output signal period, it is necessary to minimize effects of the reset flaw generated from the reset gate pulse. To that end, generally, a reset flaw period is shortened by reducing the pulse width of the reset gate pulse (RG) of FIG. 12. However, in the pulse width of the reset gate pulse, it is necessary to secure a minimum time required for sweeping the charges into the drain section.
If only the reset gate pulse width has been shortened without changing other pulse widths, as shown in FIG. 3A, a timing may be generated in which an OFF timing of the reset gate pulse 301 has phase-advanced with respect to an OFF timing of the horizontal transfer pulse H3 303.
In the case of the above described phase-advanced timing, as shown in FIG. 6B, a period for sweeping the charges by the reset gate pulse is insufficient. Thus, if a charge handled at a horizontal transfer pulse H1 section 602 is large, the defective reset is generated in which charges that cannot be discarded into a drain section 606 are left in an FD section 604. The charges left in the FD section 604 is generated as aliasing in the feed-through period, and if the CDS with the optical output signal period has been performed, image darkening in which an image is darkened more than its original brightness is generated.